Such mass memory devices are known. They have a multiplicity of mass memories, usually hard disks, and also components such as bus controllers and bridge controllers, which manage the mass memories and control the internal and external data transmissions on the basis of the requirement of servers which are connected to the mass memory devices by means of a host interface. The mass memory devices are normally used in a housing having a standard size, usually in what are known as 19″ device cabinets.
The total storage capacity of a mass memory device is determined by the dimensions of the housing cage and of the number of mass memories which are arranged within the housing cage. Hence, the number of mass memories which can be integrated within the housing cage is dependent on the size of the mass memories themselves. Progressive further development of the mass memories achieves smaller physical dimensions as the capacity becomes greater.
The servers' increasing demands on storage capacity result in the provision of further mass memory devices or at least in changeover to mass memories having a greater capacity. The result of this is that, for example when changing over from 3.5″ hard disks to 2.5″ hard disks without any significant mechanical alterations to the housing cage, the number of integratable hard disks, as shown by way of example in FIG. 3 using an insert in a device cage, in a mass memory device may be increased by a multiple. Comparing the size of the mass memories relative to one another shows that the necessary installation space for a 3.5″ hard disk in a horizontal position (interface for connection to the hard disk bus on the outside left) is equivalent to the installation space for two 2.5″ hard disks in a vertical position (interface at the bottom). In popular mass memory devices with 19″ standard system sizes, the number of available hard disks can thus be increased from 14 to at least 40.
The mass memories integrated in the external mass memory device, that is to say outside a server system, are not addressed directly via a host bus adapter in a host system, but rather can be managed using the bridge controllers and can be physically addressed by the latter. In an enterprise network environment, two bridge controllers are normally used in a mass memory device for reasons of redundancy for the system configuration used and for reasons of the number of mass memories which are to be managed. In this case, the bridge controllers can be operated differently depending on their configuration.
In an “active-active” configuration, the two bridge controllers have been activated, which means that both bridge controllers are able to access all of the mass memories integrated in the mass memory device. In this configuration, the two bridge controllers can be connected to different servers, which means that a plurality of servers can physically access a common mass memory pool and can thus be allocated to a server having greater memory resources.
In an “active-passive” configuration, only one bridge controller is ever active toward the host system and accesses all of the mass memories. The second bridge controller has an inactive status as a reserve system and is activated only in the event of failure of the active bridge controller itself. If a mass memory device has more than two bridge controllers available, these can also be operated in a mixed configuration.
Data to be stored can be stored on the mass memories on the basis of a requirement from a server connected to the mass memory device using the bridge controllers in two different ways:                in a “write back mode”, data to be stored are first written to a memory area (cache) arranged within the bridge controller and then successful storage is immediately confirmed to the server (host); however, the data are written to the mass memories at a later time, for example as soon as the appropriate mass memories are able to accept these data, or        in a “write through mode”, data to be stored are written directly to the mass memories; this is followed by acknowledgement to the server.        
In the “write back mode”, the data to be stored are available for a particular period only in the data cache memory area of the bridge controllers. For this reason, it is particularly important, for example in the event of a power failure, to protect this memory area from data losses. To this end, each bridge controller is usually provided with a BBU (Battery Backup Unit) unit.
In an “active-active” or “active-passive” configuration for a first and further bridge controller with a configured “write back mode”, the data to be stored are first written to the memory area of the bridge controller which is active for this data transaction. So that, in the event of the first bridge controller malfunctioning, the further bridge controller can adopt the full functionality transparently and without interruption, the data contents in the memory areas of the two bridge controllers need to be kept coherently. This requires permanent synchronization of the contents of the memory areas, which is known as cache coherency. This “cache synchronization” is normally performed using a data bus, usually the FC (Fiber Channel) or SCSI (Small Computer System Interface) hard disk bus.
In mass memory devices whose hard disk data bus is based, by way of example, on SAS (Serial Attached SCSI) or Serial ATA technology, some wires/lines are reserved for special purposes which could be used to reserve or set up a dedicated channel for synchronizing the data contents of the memory areas in the first and further bridge controllers. However, this is not standardized. Current standardization efforts, such as SATA II, are concentrated only on the interfaces between two bridge controllers arranged in a mass memory device.
FIG. 2 shows a known arrangement for a mass memory device 1. The mass memories 2 integrated in the mass memory device 1 can be addressed by the two bridge controllers 3. The bridge controllers 3 have internal cache memory areas 40 to which data to be stored are written in a “write back mode” configuration, and internal BBUs 5. A cache coherency bus system 60 is used to synchronize the data contents of the cache memory areas 40. The cache coherency bus system 60 is not necessarily an independent device. Often its functionality is undertaken by the hard disk bus (not shown here).
If a mass memory device 1, as shown in FIG. 4, contains a multiplicity of bridge controllers 3, each having a cache memory area 40 and a BBU 5, for managing mass memories 2, all of the bridge controllers 3 using the cache coherency bus system 60 (which again can be the hard disk bus) in order to synchronize the data contents and data status of their cache memory area 40 both when writing to the mass memories 2 and when reading from the mass memories 2.
There is a much greater level of data traffic, which has a multiple of the total bandwidth of the host interface arranged on the mass memory device for the purpose of connecting servers. In addition, a BBU needs to be provided for each bridge controller in order to protect against data losses in the event of a power failure, and this results in further costs, on the one hand, and, particularly in the case of external systems, in additional installation space being required in the mass memory device, on the other.